Ongoing trends in semiconductor device technology include miniaturization of feature size of semiconductor devices as well as increasing functional complexity of semiconductor devices. Although a feature size reduction may facilitate an increase in the number of semiconductor building blocks per unit area of a semiconductor device, e.g. a die or an integrated circuit (IC), thus facilitating more complex functionality per device, many demands for the increased functional complexity cannot be met by a single device.
Recently, this has led to the development of aggregate devices such as three-dimensional integrated circuits (3D ICs). One example of creating a 3D IC is by building electronic components and their connections in layers on a single semiconductor wafer. As a base layer of the IC is formed on a substrate, a first upper layer is formed over the base layer and is connected to the base layer using vias. Another upper layer may be formed over the first upper layer, and so on. In this way, the IC is sequentially grown layer by layer. An IC thus built is generally known as a monolithic stacked IC.
Though promising in providing density and performance benefits in advanced process nodes, such as 28 nm and below, the method of creating monolithic stacked ICs aforementioned has its own challenges. One of the challenges is directed to manufacture fault testing of monolithic stacked ICs. Conventional IC manufacture fault testing employs a known-good-die (KGD) concept where a pre-fabricated die is tested with a suite of test patterns such as supply open/short test, ground open/short test, stuck-at fault test, current consumption tests (e.g., IDDQ), timing path delay fault (or transition fault) test, etc. If a die is found with defects, it is removed from further processing, such as packaging, to save cost. The manufacture fault testing is typically enabled by some structured test architecture, such as SCAN test architecture. This KGD concept has been found less desirable in monolithic stacked IC manufacture fault testing. This is primarily due to the fact that complete logic generally spans over multiple layers in a monolithic stacked IC and complete fault testing with quality similar to or higher than KGD testing cannot be applied until all or multiple layers are built. Yet, waiting until all or multiple layers are built before applying fault testing presents a significant yield loss issue. In addition, testing of each layer during manufacturing of monolithic stacked ICs enables defect isolation and yield tracking per layer, which can be really helpful in finding layer manufacturing processing related issues.
Accordingly, an enhancement in monolithic stacked IC manufacture fault testing is needed.